Implementing a Seven-Person Voting Display Circuit Using Field-Programmable Logic Devices

DOI: https://doi.org/10.62517/jbdc.202601333

Author(s)

Jianwu Zhu1,*, Ying Zhang2

Affiliation(s)

1School of Computer Science, Wuhan City Vocational College, Wuhan, Hubei, China 2Dongfanghong Primary School, Wuhan, Hubei, China *Corresponding Author

Abstract

In scenarios such as conference voting and competition judging, simple and efficient voting devices are indispensable. Traditional discrete-circuit voting systems suffer from high hardware redundancy and poor flexibility. To optimize the design approach of voting circuits, this paper conducts a comparative study on seven-person voting circuit solutions. Two design methods are employed: one based on traditional digital discrete circuits to build hardware, and the other using an FPGA platform combined with LPM modules for programmable logic design. The results show that the discrete-circuit solution features intuitive structure and low cost but lacks scalability; in contrast, the FPGA-based solution offers high integration, convenient debugging, and reprogrammability. By comparing the strengths and weaknesses of both approaches, this study identifies suitable design strategies for different application scenarios, providing valuable references for lightweight and intelligent design of small-scale digital logic voting systems, thus demonstrating practical application value.

Keywords

FPGA; Data Selector; Adder Counter; Seven-Segment Display; Verilog; Integrated Circuit

References

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